signal clamping and ESD

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signal clamping and ESD

Postby haudio » Mon Feb 25, 2013 10:17 pm

Hi,

I'm new here, and very much inspired by your Megadrum efforts! Nice to see all the development going on. I'm trying to do my own acoustic-to-midi drum kit conversion, and so stumbled upon Megadrum. I'm fairly inexperienced with electronic networks, and looking at your schematics left me with a question.

Various methods to condition piezo signals for I/O are proposed all over the internet (i.e. voltage divide, clamping, clipping). Even at this forum i noticed some discussion on the BAT85's. What method does Megadrum use? I've drawn something (attached) that I thought was going on at the analog board, see schematic #1. Is this how its signal conditioning works?
esd.png


If so, can it also be implemented as schematic #2? A zener diode looks more straightforward (here with just an arbitrary breakdown voltage), I saw similar stuff going on at other I/O hardware. It mentioned that the capacitors may distort the high frequency signal of the piezo.
esd2.png
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haudio
 
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Re: signal clamping and ESD

Postby Maylord.war » Sun Mar 03, 2013 12:54 am

Hi,

I'm not expert but for bat's 85 i know is to protect the IC (4051) from peaks signals from piezo in series on 100ohm resistors

If you use the 4851 you don't need bat and resistors.

My two cent, regards ;)
Maylord.war
 
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